Introduction to the Paper
One of my course projects was to explore and design an analog to digital converter (ADC) and a digital to analog converter (DAC). Below, you will find a design I had completed for both an ADC and a DAC. Since the course was covering operational amplifiers (op-amps) I chose to use a flash ADC method comprised of a linear voltage ladder with a comparator at each node. The comparator is essentially an op-amp with a very high gain. So if one input is more positive than the other, the output is high. Likewise, if the other input is more positive than the first, the output is negative. The linear voltage ladder basically forms a voltage divider with many “taps”. These taps produce a reference voltage for each comparator – with each slightly less than the previous. By feeding the “sample” voltage into one input and the reference voltage into the other, the comparator is able to determine if the sample is less than or greater than the reference and output a high or low accordingly. Chaining a comparator to each of the voltage divider taps and the sample, it is possible to determine approximately what voltage the sample is (with respect to the reference). This will output a high from all comparators where the sample is greater than the reference and a low for the rest. Although this is a great start at finding the digital representation of the sample voltage, it doesn’t yet represent a true digital output. For this, the comparator output is fed into a priority encoder. The priority encoder takes the 8 inputs from the comparators and transforms them into a 3-bit representation.
To carry on with the op-amp theme in this course, I built the DAC using an op-amp as well. The op-amp is configured as a summer and adds the respective bits together with a weighted value. This weighted value is determined by the input resistor and feedback resistor values and thus the gain they produce. In this case, each bit has an input resistance of 2^(n-1)R. In this 3-bit example, the MSB of the digital signal has a gain of 1/1, the next bit is 1/2 and the LSB is 1/4. The maximum value of the analog output is subjective and depends on what the maximum voltage is for the input (usually 5 volts). The represented analog output is, however, representative of the digital input value such that 0b011 (roughly half of a 3-bit value) is .428Vcc (roughly half of the supply voltage). With higher bits of resolution, greater output accuracy can be achieved. This is met with one downfall though. It may become difficult to find odd size resistors to meet this 2^(n-1) resistor scheme. In this case, a R-2R resistor ladder may become more economical.
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This paper will focus on the analog to digital and digital to analog converter. More importantly, the operational amplifier based analog to digital and digital to analog converter. These devices are very important and important now in a modern world where virtually everything is controlled, or sensed or analyzed by a computer system. There must exist a way for an analog signal to be interpreted by a digital computer. This process is achieved by the analog to digital converter.
Not only is it important to convert an analog signal to digital, it is equally important that the digital representation is able to be converted back into the analog signal after being processed. This is the job of the digital to analog converter.
Both digital to analog and analog to digital converters are found in many different everyday devices such as televisions, computer systems and audio equipment. There are many aspects which must be considered when designing a converter of this nature. The most important, being the resolution of the conversion, be that 6-bit, 8-bit or more. The second aspect is the maximum frequency of operation, which determines the maximum input frequency that each converter is able to handle before the output no longer represents the input. In this case, the maximum frequency is determined by the slew rate of the operational amplifiers and the time it takes them to come out of saturation, as well as the propagation delay of the logic circuitry.
This paper will focus first on the analog to digital converter and then continue with the digital to analog converter. Lastly, the paper concludes with the design considerations for each type of converter
II. ANALOG TO DIGITAL CONVERTER
There are several different types of analog to digital converters that are available and each has their own advantages and disadvantages. In this paper, the flash ADC is analyzed, which is comprised of many comparators. This type of ADC is primarily used in high frequency applications such as radar and satellite communications. This reason these ADC circuits are used for high speed applications is because they don’t use capacitors to charge and discharge, which allows the circuit to operate much faster.
The flash ADC, shown in figure 1, is comprised of 2n-1 comparators with a resistor ladder network for the reference voltages. In this circuit, a 3-bit ADC is constructed, which uses 7 comparators. The output of the comparators is a thermometer-like signal, where the lower comparators (comprising of the LSB) turn on in sequential order. Normally, this would be a problem, since the output is not directly a digital signal. To correct this, the output of the comparators is put through a logic circuit, called an encoder, which turns the 7 input signals into a binary 3-bit representation.
The circuit works by taking a reference voltage, which can be any voltage that’s less than the circuit’s operational voltage, and divides it along the resistor network, which sequentially reduces the voltage in equal increments. It is important that the resistors are all equally matched as to keep within the accuracy of the ADC. The output of each voltage divider stage is fed into a different comparator, sequentially, in the non-inverting input, as seen in figure 1. The analog signal is then fed into all of the inverting inputs of the comparator. This is reversed from what is normally configured; however, the encoder circuit works by negative logic, or active low inputs. This means that for a normal logic ’1′ or high, the output is actually low. To correct for this, the inverting and non-inverting inputs are reversed.
Additionally, another adjustment that had to be made was for the open collector outputs of the comparators. They only pull the output to ground when the output is low and float the output when the output is high. Pull-up resistors were needed to correct this. The value of resistor chosen was within the specifications to provide enough current to the encoder logic as to properly trigger the input.
There were several different options when choosing a method to encode the 7 comparator outputs to a binary 3-bit output. For the simplicity of the circuit, an 8 to 3 encoder was used, which is contained on an integrated circuit. Since a normal encoder circuit would glitch when multiple input lines are active, as is the case with the comparator outputs, a special priority encoder was chosen. The priority encoder considers the most significant active input as the input signal and ignores the remaining lesser inputs.
As with the inputs, the priority encoder uses active low outputs, which normally wouldn’t be a problem, however for completeness, they are converted to active high outputs with an inverter buffer circuit. A simple transistor is used to provide the inverted output and current needed to drive the LED visual output.
To visually inspect the operation of the ADC, a potentiometer is placed at the analog input and tied between the positive and ground rails. This allows an analog input of between zero and five volts. The potentiometer is slowly turned while the digital output is verified that the binary representation does indeed range from 0 to 7 bits, sequentially.
Finally, the input to the ADC is connected to a function generator, set to produce a ramp output between zero and five volts. Each of the three binary bits are connected to a function generator to visually show the transition of the binary bits and ensure that they have equal periods. As seen in figure 2, the analog input (yellow) slowly ramps up linearly while the output bits from LSB (bottom) to MSB (middle) represent the digital output at the given voltage. Each transition occurs at equal spaces, with the exception of the bit 6, which has approximately half to third the on time that the other bits do. This is due to the resistors in the resistor network not being correctly matched to one another.
To further test the circuit, the operation frequency is increased to determine the maximum operating frequency. It appeared that 200KHz was the maximum operating frequency, where the individual binary bits where still properly changing. Beyond this frequency, the comparators could not come out of saturation quickly enough and thus the output was incorrect.
III. DIGITAL TO ANALOG CONVERSION
Like the ADC, there are many different forms of the digital to analog converter. The type of DAC discussed in this paper uses the operational amplifier to produce an analog output, which represents the digital input. There are many aspects which must be considered when designing a DAC, first of which is the number of bits that must be converted. The design considered is the weighted resister DAC, where the input of the amplifier uses a sum of the digital inputs with resistors weighted to the binary equivalent.
In this circuit, shown in figure 3, the MSB is considered resistance R and each successive bit has a value of R/2n, where n is the bit number. This type of DAC works well with small bit inputs; however larger bit inputs become difficult, where resistor values are not always available. The accuracy of these resistors must be exceptionally well matched to the calculated values for the output to be considered a well representation of the digital input.
The second type of DAC is called the R/2R method, where the input is a resistor network of R and 2R resistors for each bit, where multiple bits are cascaded, one after another. The feedback resistor is not important is more suited to select the output range of the analog signal.
This type of DAC circuit, shown in figure 3, is a current controlled voltage source, where the current into the operational amplifier produces a voltage out. Since the input to the circuit is a binary source where the voltage is always a constant value (in this case, five volts); only the number of bits changes and thus the resistor combinations change. The input resistance to the operational amplifier changes as each bit combination changes. The combination of resistors is in parallel and thus the current changes as the bits, or resistance changes. This causes the current through the feedback resistor to match the input currents. The dynamic current through the fixed resistor equates to the voltage at the output, depending on the input current. Therefore, as the input resistor combinations change, the output voltage changes too.
This circuit was tested by cascading it with the analog to digital converter, since the output was verified to be accurate. The visual analysis shows that the output of the DAC produces an analog representation as the potentiometer is changed.
The DAC output is measured with the oscilloscope, while the digital inputs are measured and triggered automatically, as shown in figure 4. The output of the DAC shows the analog nature of the signal; however there is still a noticeable stepping of the output due to the lack of resolution of the input, being only 3-bit.
IV. DESIGN CONSIDERATIONS FOR ADC AND DAC SYSTEMS
The final point to cover here is the design considerations of the ADC and DAC systems covered previously. The flash ADC is the fastest type of converter; however it comes with its own set of limitations. For one, the required comparators are 2n-1, so it can be seen that a great deal of comparators are needed to achieve a higher bit resolution. In this example, only a 3-bit comparator was used to show the principal of operation, however ideal systems are often 8-bit or larger, which would require 255 comparators at minimum. For higher bit resolution systems than 8-bit, other ADCs must be used.
This leads to the second consideration, the power requirements of the ADC. The larger number of comparators equates to an increased power consumption, which is always an issue, especially in portable electronics.
The third consideration is the maximum conversion speed. With the ADC used in this paper, it has the highest possible frequency of operation, where as other, more complicated methods utilize a capacitor to charge at a given time. As the capacitor charges based on the analog voltage, a timer is used to determine the digital value. This time needed to charge and discharge the capacitor can severely limit the operational frequency of the ADC.
The digital to analog converters do not have quite such a list of disadvantages. They rely more on precise resistor values to achieve the proper ratios. For this reason, the previously mentioned R/2R method is more common, where many precise resistors can be used, rather than specialty values that may be hard to find, if at all.
Another consideration of the DAC is the current handling at the output, which is limited to the op-amp itself. The input also generally needs a buffering circuitry to supply the needed current and proper voltages to ensure the binary values are properly represented.
 Maxim. (2001, Oct). Understanding Flash ADCs. Application Note 810. Available : http://www.maxim-ic.com/appnotes.cfm/appnote_number/810/CMP/WP-17
 Ramakant A. Gayakwad, “Op-Amps and Linear Integrated Circuits” 4th ed. New Jersey: Prentice Hall, 2000, pp. 342-346